1. Field of the Invention
The present invention relates to delay-clocked loop (DLL) circuits for synchronizing internal clock signals with external clock signals at leading/trailing edge timings.
The present application claims priority on Japanese Patent Application No. 2008-134775, the content of which is incorporated herein by reference.
2. Description of Related Art
Due to increasing high-speed processing of recent electronic systems, it is required for electronic systems to transfer data between semiconductor devices at a very high speed. For this reason, semiconductor devices such as synchronous dynamic random-access memory (SDRAM) adopt clock synchronization methods for synchronizing internal clock signals with external clock signals. SDRAM has been further developed in terms of data transfer by way of double data rate (DDR), DDR2, and DDR4, thus establishing clock synchronization at leading/trailing edges of clock signals.
Conventionally, various types of SDRAM have been designed to adopt delay-locked loop (DDL) circuits for establishing clock synchronization as disclosed in Patent Document 1, thus synchronizing timings between internal clock signals and external clock signals.                Patent Document 1: Japanese Unexamined Patent Application Publication No. 2003-91331        
FIG. 5 shows an example of the DLL circuit using CMOS transistors as disclosed in Patent Document 1. The DLL circuit of FIG. 5 includes a coarse delay circuit 10 in which a plurality of delay elements 11 is connected together in a cascade-connection manner. The coarse delay circuit 10 is referred to as a coarse delay line, which delays a reference clock signal input thereto by a desired delay time so as to output a delay signal from a selected tap from among a plurality of taps having different delay times.
A multiplexer 12 is a switching unit for selecting one of odd-phase signals extracted from odd-numbered taps of the coarse delay circuit 10, while a multiplexer 13 is a switching unit for selecting one of even-phase signals extracted from even-numbered taps of the coarse delay circuit 10. A fine delay circuit 18 serves as an interpolation circuit receiving an odd-phase signal O0 and an even-phase signal E0 output from the multiplexers 12 and 13, thus producing an output clock signal. A phase detection circuit 21 detects a phase difference between the reference clock signal and the output clock signal of the fine delay circuit 18, thus outputting a phase detection result to a delay control circuit 22. Based on select signals output from the delay control circuit 22, the multiplexer 12 selects a desired odd-numbered tap of the coarse delay circuit 10, while the multiplexer 13 selects a desired even-numbered tap of the coarse delay circuit 10. In response to a control signal output from the delay control circuit 22, the fine delay circuit 18 changes an internal division on the phase difference between the reference clock signal and the output clock signal. FIG. 5 omits a generally-known constitution in which the output clock signal is supplied to a replica circuit, the output signal of which is then fed back to the phase detection circuit 21. By way of this constitution, the DLL circuit of FIG. 5 adjusts the phase of the reference clock signal in correspondence with a delay time adapted to the replica circuit.
FIG. 6 shows an example of the detailed constitution of the DLL circuit of FIG. 5, in which a plurality of coarse delay lines CDL 101 to 104 (corresponding to the coarse delay circuit 10) is connected to a plurality of multiplexers 205 to 208 (corresponding to the multiplexers 12 and 13) and a fine delay line FDL 210 (corresponding to the fine delay circuit 18).
In FIG. 6, a CDL 201 outputs a zero odd-phase signal COUTO0 and a zero even-phase signal COUTE0; then, subsequent to the CDL 201, a CDL 202 outputs a first odd-phase signal COUTO1 and a first even-phase signal COUTE1. Subsequent to the CDL 202, a CDL 203 outputs a second odd-phase signal COUTO2 and a second even-phase signal COUTE2; then, subsequent to the CDL 203, a CDL 204 outputs a third odd-phase signal COUTO3 and a third even-phase signal COUTE3. The zero to third odd-phase signals COUTO0 to COUTO3 are supplied to the multiplexer 205, in which one of them is selected in response to the select signal of the delay control circuit 22. The zero to third even-phase signals COUTE0 to COUTE3 are supplied to the multiplexer 206, in which one of them is selected in response to the select signal of the delay control circuit 22. The odd-phase signal selected by the multiplexer 205 is supplied to the multiplexer 207 so as to output a signal FINO, while the even-phase signal selected by the multiplexer 206 is supplied to the multiplexer 208 so as to output a signal FINE. The signals FINO and FINE are supplied to the interpolation circuit 210.
FIG. 7 shows a single coarse delay line (CDL) shown in FIG. 6, wherein CMOS gate circuits are used for inverters forming delay elements. Specifically, an inverter 211 for receiving an input signal CDLj is followed by seven pairs of inverters (i.e. seven inverter pairs corresponding to seven delay stages) 212-213, 214-215, 216-227, 218-219, 220-221, 222-223, and 224-225 and is finally connected with an inverter 226, thus outputting a signal CDLj+1.
The output terminal of the inverter 211 receiving the input signal CDLj is connected to a tri-state inverter (or a clocked inverter) 311 whose output terminal is connected to the even-numbered inverter pairs (i.e. the inverter pairs consisting of 214-215, 218-219, and 222-223) via tri-state inverters 313, 315, and 317 and is finally connected to a buffer 227, the output terminal of which is connected to an odd-phase output terminal COUTOj.
The output terminal of the inverter pair consisting of 212-213 is connected to a tri-state inverter 312 whose output terminal is connected to the odd-numbered inverter pairs (i.e. the inverter pairs consisting of 216-217, 220-221, and 224-225) via tri-state inverters 314, 316, and 318 and is finally connected to a buffer 228, the output terminal of which is connected to an even-phase output terminal COUTEj.
In the above, two output signals whose delay times correspond to two inverter pairs are output from the output terminals COUTOj and COUTEj.
The foregoing coarse delay circuit 10 generates two delay signals per every two inverter pairs (or every two delay stages), wherein the signals having delay times corresponding to two delay stages are output from the selected odd-numbered inverter pair and the selected even-numbered inverter pair. The two delay signals having different timings are subjected to interpolation in the fine delay circuit 18, thus achieving high-precision phase adjustment.
Since the two delay signals are output from the coarse delay circuit 10 with a delay difference corresponding to at least two inverter pairs therebetween, the fine delay circuit 18 needs to perform interpolation with respect to the delay difference corresponding to at least two inverter pairs.
That is, two signals E0 and O0 having the phase difference corresponding to the two inverter pairs therebetween are subjected to interpolation, thus producing an interpolation signal MIX0_T shown in FIG. 8. When the delay control circuit 22 determines a mixing factor of 100% with respect to the signal E0, the trailing edge of the interpolation signal MIX0_T depends upon the signal E0 only. When the delay control circuit 22 determines a mixing factor of 100% with respect to the signal O0, the trailing edge of the interpolation signal MIX0_T depends upon the signal D0 only. Thus, the trailing edge of the interpolation signal MIX0_T (i.e. the trailing-edge timing of the mixed signal MIXOUT) is determined based on the mixing factor between the signals E0 and D0. In this connection, the leading-edge timing of the mixed signal MIXOUT is determined by another interpolation circuit (for interpolating an inverse-phase signal).
In order to linearly interpolate the signals E0 and D0 having a phase difference 2tD therebetween (where tD denotes a delay time of each inverter pair), the interpolation signal MIX0_T needs a time of 2tD or more to be discharged from VDD to a threshold value VDD/2. In addition, another time of 2tD is necessary to cope with the phase difference between the signals E0 and D0, and a further time of 2tD is necessary for the interpolation signal MIX0_T to be decreased to VSS; hence, a total time of 6tD is required for the interpolation at the trailing edge of the interpolation signal MIX0_T. In order to achieve interpolation on both sides (i.e. both the leading edge and the trailing edge), the interpolation circuit requires a minimum operation cycle tCYC=12tD, which in turn regulates the maximum operation frequency of the DLL circuit. In order to increase the maximum operation frequency of the DLL circuit, it is necessary to decrease the minimum operation cycle tCYC of the interpolation circuit.
The present inventor has recognized that the foregoing DLL circuit performs interpolation on signals having the phase difference corresponding to at least the two inverter pairs (composed of CMOS gate circuits) therebetween, resulting in increasing the minimum operation cycle tCYC of the interpolation circuit and thus regulating the maximum operation frequency of the DLL circuit. The present inventor asserts that the minimum operation cycle tCYC of the interpolation circuit should be decreased in order to increase the maximum operation frequency of the DLL circuit.